DocumentCode
2762797
Title
A programmable BIST architecture for clusters of multiple-port SRAMs
Author
Benso, Alfredo ; Di Carlo, S. ; Di Natale, G. ; Prinetto, Olo ; Lobetti Bodoni, M.
Author_Institution
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
fYear
2000
fDate
2000
Firstpage
557
Lastpage
566
Abstract
This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing
Keywords
SRAM chips; built-in self test; fault diagnosis; integrated circuit testing; memory architecture; microprogramming; March algorithm; background pattern generator; fault diagnosis; memory architecture; memory wrappers; multiple-port SRAM clusters; programmable BIST architecture; single microprogrammable BIST processor; Access protocols; Automatic generation control; Built-in self-test; Communication networks; Memory management; Random access memory; Read-write memory; System testing; Test pattern generators; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2000. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-6546-1
Type
conf
DOI
10.1109/TEST.2000.894249
Filename
894249
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