A fast, asP*, RGD arbiter

Author

Greenstreet, Mark R. ; Ono-Tesfaye, Tarik

fYear

1999

fDate

1999

Firstpage

173

Lastpage

185

Abstract

This paper presents the design of a high-throughput, low-latency, asP*, RGD arbiter. Spice simulations for an implementation in a 0.8 μ CMOS process show a request-to-grant delay of 0.74 ns and a done-to-grant-delay of 0.42 ns. Maximum throughput of requests from a single client is one grant per 1.8 ns; if both clients make request aggressively, the arbiter can produce one grant per 1.2 ns. In addition to presenting a high-performance design, this paper examines trade-offs in performance driven design. In particular, logic delay seems to dominate metastability concerns when optimizing performance

Keywords

CMOS logic circuits; SPICE; asynchronous circuits; circuit stability; delays; logic CAD; pipeline processing; 0.42 ns; 0.74 ns; 0.8 micron; CMOS process; Spice simulations; done-to-grant-delay; high-performance design; logic delay; low-latency asP* RGD arbiter; metastability concerns; performance driven design; request throughput; request-to-grant delay; Application specific processors; CMOS process; Circuits; Clocks; Delay; Design optimization; Logic design; Metastasis; Synchronization; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings., Fifth International Symposium on

Conference_Location

Barcelona

ISSN

1522-8681

Print_ISBN

0-7695-0031-5

Type

conf

DOI

10.1109/ASYNC.1999.761532

Filename

761532