DocumentCode
2762801
Title
A built-in self-repair analyzer (CRESTA) for embedded DRAMs
Author
Kawagoe, Tomoya ; Ohtani, Jun ; Niiro, Mitsutaka ; Ooishi, Tukasa ; Hamada, Mitsuhiro ; Hidaka, Hideto
Author_Institution
ULSI Dev. Center, Mitsubishi Electr. Corp., Itami, Japan
fYear
2000
fDate
2000
Firstpage
567
Lastpage
574
Abstract
A new practical built-in self-repair analyzer algorithm for embedded DRAMs (e-DRAM) achieves 100% detection ability of the repairable chips with 1% area penalty of the target 32 Mb embedded DRAM by 4 parallel analyzers. It works at as fast as 500 MHz, well beyond targeted e-DRAMs´ maximum operation speed around 200 MHz+
Keywords
DRAM chips; automatic test pattern generation; built-in self test; embedded systems; integrated circuit testing; 32 Mbit; 500 MHz; BIST; CRESTA; algorithmic pattern generator; built-in self-repair analyzer; embedded DRAM; hardware CAM; parallel analyzers; repairable chips; small die size penalty; Algorithm design and analysis; Automatic testing; Built-in self-test; Costs; Failure analysis; Large scale integration; Manufacturing; Production management; Random access memory; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2000. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-6546-1
Type
conf
DOI
10.1109/TEST.2000.894250
Filename
894250
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