VLSI implementation of low-power cost-efficient lossless ECG encoder design for wireless healthcare monitoring application

An efficient VLSI architecture of a lossless ECG encoding circuit is proposed for wireless healthcare monitoring applications. To reduce the transmission and storage data, a novel lossless compression algorithm is proposed for ECG signal compression. It consists of a novel adaptive rending predictor and a novel two-stage entropy encoder based on two Huffman coding tables. The proposed lossless ECG encoder design was implemented using only simple arithmetic units. To improve the performance, the proposed ECG encoder was designed by pipeline technology and implemented the two-stage entropy encoder by the architecture of a look-up table. The VLSI architecture of this work contains 3.55 K gate counts and its core area is 45987 μm² synthesised by a 0.18 μm CMOS process. It can operate at 100 MHz processing rate with only 36.4 μW. The data compression rate reaches an average value 2.43 for the MIT-BIH Arrhythmia Database. Compared with the previous low-complexity and high performance techniques, this work achieves lower hardware cost, lower power consumption, and a better compression rate than other lossless ECG encoder designs.