Optimizing the flattened test-generation model for very large designs

Author

Wohl, Peter ; Waicukauski, John

Author_Institution

Synopsys Inc., Williston, VT, USA

fYear

2000

fDate

2000

Firstpage

681

Lastpage

690

Abstract

Design and test tools, such as automatic test-pattern generators (ATPG) and fault-simulators, work on a “flattened” simulation model of the entire design. Run-time performance is directly influenced by the number and complexity of simulation primitives in the flattened model. Moreover, the memory required to flatten and store the simulation model of current multi-million-gate designs may exceed the available address space of 32 bit computers. We present several model-optimization techniques that significantly reduce the number of simulation primitives and the associated memory usage while still preserving a complete, highly efficient flattened model. A commercial ATPG product implementing these techniques demonstrates fast simulation model construction for very large designs using a relatively small memory space

Keywords

VLSI; automatic test pattern generation; digital simulation; electronic engineering computing; fault simulation; integrated circuit testing; logic testing; optimisation; ATPG; automatic test-pattern generators; fast simulation model construction; fault-simulators; flattened simulation model; flattened test-generation model optimisation; memory usage reduction; model-optimization techniques; run-time performance; simulation primitives reduction; very large designs; Automatic test pattern generation; Automatic testing; Computational modeling; Computer simulation; Costs; Design optimization; Discrete event simulation; Memory management; Runtime; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2000. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-6546-1

Type

conf

DOI

10.1109/TEST.2000.894263

Filename

894263