Accurate measurement of high-speed package and interconnect parasitics

The feasibility of using high-speed wafer probes to measure accurately the parasitics associated with packages and interconnects used in conjunction with high-speed integrated circuits is demonstrated. A way of calibrating out the fixture-related errors while providing a reconfigurable mechanical interface to specific points of interest is demonstrated. These points can be at the perimeter and also internal. Calibration at the point of interface to the structure under test and a well-controlled mechanical interface enable large numbers of highly repeatable measurements to be made easily and accurately. The effect is to extend the full capability of test instrumentation to the physical points of interest, with accuracy and repeatability from site to site. The ability to calibrate at the probe tips is necessary to eliminate distortions from cables and probes. Some sources of errors, such as crosstalk, should be minimized in the probe, since they are difficult to correct in most cases