Bridging fault extraction from physical design data for manufacturing test development

In this paper we explore the process of extracting potential bridging fault sites from the physical design database for VLSI devices by using standard extraction tools for fringe and overlap capacitance. We then use the extracted capacitance to create a list of potential bridging fault sites ordered to reflect the relative probability of a bridging fault occurring at each site. As a result, potential bridging fault sites can be rank-ordered for manufacturing test development such that the most likely site can be targeted first. In this way we improve the overall efficiency and effectiveness of the test development process. We have implemented this technique for the Delta 39K^TM series of complex programmable logic devices by Cypress Semiconductor and describe the results obtained