Hierarchical Strategy of Model Partitioning for VLSI-Design Using an Improved Mixture of Experts Approach

Author

Hering, K. ; Haupt, R. ; Villmann, Th.

Author_Institution

Universitdt Leipzig, Inst. fur Informatik, Germany

fYear

1996

fDate

22-24 May 1996

Firstpage

106

Lastpage

113

Keywords

Bipartite graph; Buildings; Clocks; Genetics; Hardware; Logic design; Logic testing; Microprocessors; Partitioning algorithms; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Simulation, 1996. Pads 96. Proceedings. Tenth Workshop on

Conference_Location

Philadelphia, PA, USA

Print_ISBN

0-8186-7539-X

Type

DOI

10.1109/PADS.1996.761568

Filename

761568

Link To Document