Universal test generation using fault tuples

Author

Desineni, Rao ; Dwarkanath, Kumar N. ; Blanton, R.D.

Author_Institution

Center for Electron. Design Autom., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

2000

fDate

2000

Firstpage

812

Lastpage

819

Abstract

A test generation tool for combinational circuits called FATGEN has been developed based on the notion of fault tuples. FATGEN can be used to simultaneously generate tests for many types of misbehavior that occur in digital systems. Individual experiments involving SSL, transistor stuck-open, path delay and bridging faults for the ISCAS85 benchmark circuits reveal an average speedup of nearly 32% and test set compaction of 60% when faults of all types are analyzed simultaneously. In addition, there is an average reduction of approximately 34% in the number of aborted faults

Keywords

automatic test pattern generation; combinational circuits; data structures; digital integrated circuits; fault diagnosis; integrated circuit testing; logic testing; ATPG; FATGEN; IC testing; ISCAS85 benchmark circuits; SSL; aborted faults; bridging faults; combinational circuits; fault tuples; macrofault; path delay; single stuck line model; test set compaction; transistor stuck-open; universal test generation; CMOS technology; Circuit faults; Circuit testing; Digital systems; Electrical fault detection; Electronic design automation and methodology; Engines; Semiconductor device modeling; System testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2000. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-6546-1

Type

conf

DOI

10.1109/TEST.2000.894283

Filename

894283