An on-chip low power clock multiplier unit in 0.25 micron technology

A new method to obtain a high frequency clock (1 GHz) from a low frequency reference clock (10 MHz) is presented in this paper. High frequency is achieved using two level sensitive flip-flops. Variable delay lines are used to ensure that the multiplied clock is running in correct frequency. In the newly designed multiplier, the low frequency reference clock itself at every of its falling and rising edge keeps the generated high frequency clock in phase. The clock multiplication is achieved with 82 ps peak-to-peak jitter when the generated clock is 1 GHz and consuming 0.822 mW power from 2.5 volt power supply. The performance of the multiplication unit is tested on PSPICE using BSIM3v3 model parameters in .25 mum CMOS technology