DocumentCode
2763487
Title
Fault distinguishing pattern generation
Author
Bartenstein, Tom
Author_Institution
TestBench Dev., IBM Corp., USA
fYear
2000
fDate
2000
Firstpage
820
Lastpage
828
Abstract
Test Generation for VLSI circuits suffers from two competing goals-to reduce the cost of test by minimizing the number of tests, and to be able to diagnose errors when failures occur. This paper outlines a methodology for generating diagnostic test patterns as they are needed using standard ATPG took. These diagnostic patterns are guaranteed to provide better diagnostic resolution than traditional manufacturing test patterns, and the use of standard ATPG fools enables generation of diagnostic patterns only when these patterns are needed
Keywords
VLSI; automatic test pattern generation; fault diagnosis; integrated circuit testing; logic testing; production testing; VLSI circuits; cost; diagnostic patterns; diagnostic resolution; diagnostic test patterns; errors; manufacturing test patterns; minimisation; standard ATPG; standard ATPG fools; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Costs; Logic testing; Manufacturing; Software testing; Test pattern generators; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2000. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-6546-1
Type
conf
DOI
10.1109/TEST.2000.894285
Filename
894285
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