Test chips for the evaluation of the performance of IC packaging and interconnection technologies

Author

Mathuna, Cian O.

Author_Institution

Nat. Microelectronics Res. Centre, Univ. Coll., Cork, Ireland

fYear

1989

fDate

26-28 Apr 1989

Firstpage

286

Lastpage

289

Abstract

Three test chips that can be used to evaluate IC packaging technologies either at the development stage or as process control tools in a manufacturing environment is described. Structures have been incorporated in the test chips for the characterization of packaging technologies in terms of their environmental and mechanical reliability, thermal resistance, and electrical performance. The author describes the potential application of the test chips in a manufacturing environment for process control of die-attach material and of moisture content in hermetic package sealing. The application of one of the test chips to electrical characterization of high-pin-count packaging technologies is presented

Keywords

integrated circuit testing; moisture measurement; packaging; production testing; reliability; seals (stoppers); IC packaging; development stage; die-attach material; electrical characterization; electrical performance; hermetic package sealing; high-pin-count packaging technologies; interconnection technologies; manufacturing environment; mechanical reliability; moisture content; process control tools; test chips; thermal resistance; CMOS technology; Circuit testing; Diodes; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit technology; Integrated circuit testing; Materials testing; Process control; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Manufacturing Technology Symposium, 1989, Proceedings. Japan IEMT Symposium, Sixth IEEE/CHMT International

Conference_Location

Nara

Type

conf

DOI

10.1109/IEMTS.1989.76158

Filename

76158