Deception by design: fooling ourselves with gate-level models

Author

Rearick, Jeff ; Maxwell, Peter

fYear

2000

fDate

2000

Firstpage

921

Lastpage

929

Abstract

The distortion of test coverage statistics by overly simplistic circuit and fault models is explored. It is shown that the artificially high single stuck-at coverage reported on traditional gate-level models results in the omission of test patterns essential to achieve full coverage. The problem lies not directly with the fault model, but instead with the gate models and test generator assumptions used. The necessity of two-pattern tests is demonstrated on simple library cells, and the stuck-at coverage improvement measured on benchmark circuits is shown to average 33%. The need for a superior fault model is explained

Keywords

CMOS logic circuits; application specific integrated circuits; automatic test pattern generation; fault diagnosis; integrated circuit modelling; integrated circuit testing; ASIC test patterns; ATPG; CMOS logic; benchmark circuit; gate-level models; library cells; simplistic circuit models; simplistic fault models; single stuck-at coverage; test coverage statistics; test generator assumptions; test pattern omission; two-pattern tests; Application specific integrated circuits; Automatic test pattern generation; Automatic testing; Benchmark testing; CMOS logic circuits; Circuit faults; Circuit testing; Logic gates; Logic testing; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2000. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-6546-1

Type

conf

DOI

10.1109/TEST.2000.894303

Filename

894303