On the simulation of stochastic iterative decoder architectures

The advent of Shannon capacity-approaching error control codes such as turbo codes and low density parity check (LDPC) codes has been revolutionary, leading to their incorporation into numerous recent digital communications standards. The key to exploiting the power of these codes is the utilization of an iterative decoder. While high error-correcting performance iterative decoder architectures are known, the complexity normally increases commensurately with the performance. Increased area and power consumption, the consequences of great complexity, are undesirable, particularly so in mobile wireless applications. We have previously proposed a novel architecture to realize a high-performance, low-complexity iterative decoder using stochastic computational elements. Using stochastic computation, it should be possible to construct iterative decoders that feature both high performance and low complexity with little compromise. In this paper we present a tutorial introduction to stochastic iterative decoding. We then discuss aspects of our new bit-true decoder simulation software, including its flexibility for testing architectural variations, reusability for other projects, and performance results