Threshold voltage shift in 0.1 μm self-aligned-gate GaAs MESFETs under bias stress and related degradation of ultra-high-speed digital ICs

Author

Fukai, Yoshino K. ; Yamasaki, Kimiyoshi ; Nishimura, Kazumi

Author_Institution

NTT Syst. Electron. Lab., Kanagawa, Japan

fYear

1999

fDate

1999

Firstpage

116

Lastpage

120

Abstract

Bias-temperature stress examinations of self-aligned 0.1 μm-length gate GaAs MESFETs have revealed a threshold voltage shift related to the dopant concentration near the gate sides. A 100 mV increase in threshold voltage in the FETs leads to a 20% reduction of operating speed in digital ICs after 1000 hr forward-biased storage at 200°C. The degradation is released by increasing the carrier density near the gate edges. We predict a median life exceeding 10⁶ hours at 100°C by setting the Si dose as high as 4×10¹³ cm^-2

Keywords

III-V semiconductors; MESFET integrated circuits; Schottky gate field effect transistors; carrier density; doping profiles; environmental degradation; field effect digital integrated circuits; gallium arsenide; integrated circuit reliability; semiconductor device testing; thermal stresses; very high speed integrated circuits; 0.1 micron; 100 C; 1000 hr; 1000000 hr; 200 C; GaAs; GaAs MESFETs; Si dose; bias stress; bias-temperature stress tests; digital ICs; forward-biased storage; gate edge carrier density; gate length; gate side dopant concentration; median device life; operating speed; self-aligned-gate GaAs MESFETs; threshold voltage; threshold voltage shift; ultra-high-speed digital IC degradation; ultra-high-speed digital ICs; Circuits; Degradation; FETs; Gallium arsenide; Gold; MESFETs; Ohmic contacts; Optical refraction; Stress; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 1999. 37th Annual. 1999 IEEE International

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5220-3

Type

conf

DOI

10.1109/RELPHY.1999.761602

Filename

761602