Title :
A good excuse for reuse: “open” TAP controller design
Abstract :
In this paper we present a design for IEEE 1149.1 Test Access Port (TAP) controllers that is based on a practical reuse methodology. While the basic use and core functionality of TAP controllers are standardized, the RTL structure and user refinements of TAPs can vary widely leading to incompatibilities and difficulties in reusing TAP controller IP across designs and between DFT suppliers. Upon study, we find that the TAP controller is an ideal candidate for reuse. From the definitions and guidelines of the IEEE Standard we can construct a core architecture of required modules and fully define their interfaces. With the addition of a few simple usage and design guidelines, we can then define an “open architecture” TAP controller that facilitates rapid, automatic customization with a library of modular enhancements
Keywords :
IEEE standards; boundary scan testing; built-in self test; design for testability; integrated circuit testing; software reusability; BIST methodology; IEEE 1149.1 Test Access Port controllers; RTL structure; TAP controllers; boundary register control; boundary scan architecture; core architecture; core functionality; design; design guidelines; interface definition; modular enhancement library; open architecture TAP controller; rapid automatic customization; resource contention; reuse methodology; user refinements; Automatic control; Built-in self-test; Circuit testing; Clocks; Guidelines; Integrated circuit technology; Integrated circuit testing; Libraries; Logic testing; Signal design;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894322