On-the-shelf core pattern methodology for ColdFire(R) microprocessor cores

This paper describes how pattern sets are chosen and put on-the-shelf for ColdFire hard microprocessor cores. Some considerations are the frequency of the pattern set, the number of each type of pattern set needed and the format in which the patterns are saved. These decisions must be made without the knowledge of restrictions that will be on the device in which the core will be embedded. Restrictions such as the tester frequency and memory limitations, the pad frequency limitations and the package pin and power limitations are discussed. The pattern set must be flexible enough to address many of these issues “on the fly”. How the pattern set is chosen for the hard core and how it is made flexible are the challenges addressed in this paper