On-the-shelf core pattern methodology for ColdFire(R) microprocessor cores

Author

McLaurin, Teresa L. ; Potter, John C.

Author_Institution

Motorola Inc., Austin, TX, USA

fYear

2000

fDate

2000

Firstpage

1100

Lastpage

1107

Abstract

This paper describes how pattern sets are chosen and put on-the-shelf for ColdFire hard microprocessor cores. Some considerations are the frequency of the pattern set, the number of each type of pattern set needed and the format in which the patterns are saved. These decisions must be made without the knowledge of restrictions that will be on the device in which the core will be embedded. Restrictions such as the tester frequency and memory limitations, the pad frequency limitations and the package pin and power limitations are discussed. The pattern set must be flexible enough to address many of these issues “on the fly”. How the pattern set is chosen for the hard core and how it is made flexible are the challenges addressed in this paper

Keywords

automatic test pattern generation; critical path analysis; embedded systems; fault diagnosis; integrated circuit testing; logic testing; microprocessor chips; ATPG tool; ColdFire hard microprocessor cores; embedded core; fault coverage; memory limitations; on-the-shelf core pattern methodology; package pin limitations; pad frequency limitations; pattern sets; power limitations; tester frequency; Automatic test pattern generation; Delay; Frequency; Logic design; Logic testing; Microprocessors; Packaging; System testing; Time to market; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2000. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-6546-1

Type

conf

DOI

10.1109/TEST.2000.894323

Filename

894323