Simulation of electromigration damage in chip level interconnect lines: a grain structure based statistical approach

Reliability assessment of chip level interconnects is based on accelerated testing at a higher temperature and a larger current density than expected in service conditions. The critical parameters needed to extrapolate accelerated test data to service conditions are the activation energy, Q, and the current density exponent, n. Although current density exponents and activation energies are well-known for elemental processes (like void nucleation due to electromigration generated stress), there is no consensus on which apparent activation energy or current density exponent values would be applicable in reliability estimates for realistic line structures. Here, we first review our electromigration simulation tool. We then apply the electromigration simulation tool to statistical lifetime analysis of realistic line structures generated by a Monte-Carlo algorithm. For a given grain structure distribution, the stress evolution along the line is simulated, letting voids nucleate at the sites where the stress exceeds a critical level, and the nucleated voids are then allowed to grow till the largest one reaches the preset critical size, resulting in a `failure´ of the particular line. By repeating this process for various current densities and temperatures, it becomes possible to extract the apparent activation energies and current density exponents from the simulation data