Run-time reconfigurable hardware blocks for multimedia applications

In this paper, we build on an ongoing project that consists of a run-time reconfigurable system-on-chip (RTR-SoC) and we target it for multimedia applications. This is achieved by designing several hardware blocks (HBs) that can be reconfigured at run-time by the aforementioned system. The latter enables the HBs to execute simultaneously in a multi-purpose environment. The HB functions consist primarily of image processing operations, including 2D high-pass and low-pass image filters and basic digital watermarking algorithms. We conclude with preliminary results of the HB, including simulation results of the HB interface when the latter is accessed by several sources simultaneously