A new pipeline design for binarization and thinning of fingerprint images

Two critical steps in fingerprint recognition are binarization and thinning of the image. The need for real-time processing led us to local adaptive thresholding approach for the binarization step. We introduce a new hardware for this purpose based on pipeline architecture. We propose a method for selecting an optimal block size for the thresholding purpose and then the binarized image is dilated. We also present a new pipeline structure for implementing the thinning algorithm. The suggested structure was implemented using Vertix II FPGAs from Xilinx Corporation. The processing time for a 572*572 image is about 1.45 milliseconds