Uniaxial and Biaxial Strain for CMOS Performance Enhancement

Author

Nguyen, B.-Y. ; Zhang, Shaoting ; Thean, A. ; Grudowski, P. ; Vartanian, V. ; White, T. ; Zollner, S. ; Theodore, D. ; Goolsby, B. ; Desjardins, H. ; Prabhu, L. ; Garcia, Raul ; Hackenberg, J. ; Dhandapani, V. ; Murphy, Sinead ; Rai, Rajesh ; Conner, J. ;

Author_Institution

Freescale Semicond. Inc., Technol. Solutions Organ., Austin, TX

fYear

2006

fDate

15-17 May 2006

Firstpage

1

Lastpage

3

Abstract

Uniaxial stressors have been mainly employed for boosting PMOS performance, while it is more difficult to increase NMOS performance using tensile stressors. This results in changing the n:p ratio, which requires circuit layout changes. Enhancing both NMOS and PMOS performance to retain the same n:p ratio is desirable. Interactions between biaxial lattice strain, uniaxial relaxation, process-induced stressor and channel orientation have been optimized to achieve the desired stress configurations for enhancing both short-channel SSOI NMOS and PMOS devices

Keywords

MOSFET; semiconductor device testing; stress effects; stress relaxation; CMOS performance enhancement; NMOS performance; PMOS performance; SSOI NMOS devices; SSOI PMOS devices; biaxial lattice strain; biaxial strain; channel orientation; n:p ratio; process-induced stressor; tensile stressors; uniaxial relaxation; uniaxial strain; uniaxial stressors; Capacitive sensors; Germanium silicon alloys; Lattices; Silicon germanium; Strain measurement; Substrates; Tensile strain; Tensile stress; Uniaxial strain; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SiGe Technology and Device Meeting, 2006. ISTDM 2006. Third International

Conference_Location

Princeton, NJ

Print_ISBN

1-4244-0461-4

Type

conf

DOI

10.1109/ISTDM.2006.246545

Filename

1716039