A continuous time synapse employing a refreshable multilevel memory

VLSI constraints affect hardware electronic neural systems. Some architectural modifications are discussed. Hardware implementation of neural networks is required to achieve real-time performance. The architecture is dominated by the size and performance of the synapse, and therefore its design is critical to a dense neural architecture. The major problem in designing an analog synapse is the development of an analog memory. Several possible analog memories have been proposed, but for many applications, dynamic refreshing schemes allow the best overall performance. Dynamic refreshing schemes potentially allow very compact synapses with fast read and write operations. The system presented employs a very dense synapse that allows dynamic refreshing of 8 to 10 bit accuracy with a 1 μs refresh/read time using a 2-MHz, successive approximation, analog/digital-digital/analog converter. The synapse size is 95 μm×70 μm for a 2 μm process