Title :
CMOS combinational logic design for GaAs heterostructure MOSFET technology
Author :
Paluchowski, Sonia H. ; Milgrew, Mark J. ; Roy, Scott ; Cumming, David R S
Author_Institution :
Univ. of Glasgow, Glasgow
Abstract :
In this paper, we evaluate the impact of GaAs MOSFET technology on the design of CMOS combinational logic. A BSIM model is developed for both GaAs pMOS and nMOS transistors based on the underlying device physics, drift-diffusion simulations, and measured data. An elementary family of logic gates are implemented using these models and a set of optimal transistor sizing ratios are established. This is achieved by adopting a delay model that minimises the average rise and fall times of the logic gates.
Keywords :
CMOS logic circuits; MOSFET; circuit simulation; combinational circuits; gallium arsenide; logic design; logic gates; CMOS combinational logic design; GaAs; delay model; drift-diffusion simulation; heterostructure MOSFET technology; logic gate; nMOS transistor; pMOS transistor; CMOS logic circuits; CMOS technology; Delay; Gallium arsenide; Logic design; Logic devices; Logic gates; MOSFET circuits; Physics; Semiconductor device modeling;
Conference_Titel :
Optoelectronic and Microelectronic Materials and Devices, 2006 Conference on
Conference_Location :
Perth, WA
Print_ISBN :
978-1-4244-0578-7
Electronic_ISBN :
978-1-4244-0578-7
DOI :
10.1109/COMMAD.2006.4429875
