A High Performance Scalable FFT

An FPGA implementation of a fast Fourier transform (FFT) circuit is described as an example of a new class of parallel FFT architectures that can provide better performance and functionality than traditional pipelined FFTs and is well suited to wireless applications. Any circuit implementation can perform any transform size that is a multiple of 256 as long as adequate memory is provided. Throughput can be adjusted by adding/subtracting identical blocks of hardware. Power is minimized by using only small memories, providing systolic data flow to avoid memory reads/writes, and localizing connections to reduce interconnect overhead. High dynamic range is obtained through a unique multiple block floating point (BFP) feature. The design is regular in structure and is built with only three simple cells. An FPGA based demonstration circuit with 89db signal-to-quantization-noise has been implemented that can perform a 256-point transform continuously at 0.66 musec/transform. Circuit comparisons are made with a modern commercial pipelined FFT.