Title :
Design and implementation of floating point multiplier based on Vedic Multiplication Technique
Author :
Kanhe, A. ; Das, Sajal K. ; Singh, A.K.
Author_Institution :
Dept. of Electron. & Telecomm, KITE Raipur, Raipur, India
Abstract :
In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyakbhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in VHDL and Virtex-5 FPGA is used.
Keywords :
IEEE standards; field programmable gate arrays; floating point arithmetic; hardware description languages; logic design; multiplying circuits; IEEE 754 32-bit format; IEEE 754 floating point multiplier design; IEEE 754 floating point multiplier implementation; Urdhva-triyakbhyam sutra; VHDL; Vedic multiplication technique; Virtex-5 FPGA; mantissa multiplication; over-flow cases; underflow cases; Adders; Computers; Conferences; Delay; Erbium; Field programmable gate arrays; Standards; FPGA; Floating Point multiplier; Urdhva-triyakbhyam sutra; Vedic Mathematics;
Conference_Titel :
Communication, Information & Computing Technology (ICCICT), 2012 International Conference on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4577-2077-2
DOI :
10.1109/ICCICT.2012.6398204
