High performance coding systems for digital transmission of TV and HDTV signals

The studies performed in the framework of CMTT/2 for the transmission of 4:2:2 video signals through digital networks, have led to the definition of a bitrate reduction algorithm. In order to implement this videoalgorithm on a single board, a considerable effort has been made to develop an ASIC chipset, capable of processing 27 M samples per second (4:2:2 picture). For HDTV signals, the same technique can be used to provide a bitrate reduction from 1.152 Gbit/s to about 120 Mbit/s. This compression algorithm allows the transmission of one HDTV channel with audio and service channels on a 139.264 Mbit/s (or 2×34.368 Mbit/s) G703/G751 link or on an ATM network (155.5 Mbit/s). The authors describe the hardware implementation of the chipset in TV and HDTV codecs; emphasis is put to the features and performances of the equipment