Title :
Low leakage nanoscaled Body on Insulator FinFET with underlap and high k dielectric
Author :
Bukkawar, Sarika ; Sarwade, Nisha
Author_Institution :
Electr. Dept., Mumbai Univ., Mumbai, India
Abstract :
In this paper Body over Insulator (BOI) FinFET structure where the channel region is insulated from body by buried oxide and with underlap is studied. An extensive simulation study and analysis of the effect of underlap with SiO2 and Si3N4 dielectrics on BOI FinFET has been performed using the TCAD SILVACO (DevEDIT 3D,ATLAS). The simulation results has revealed that BOI FinFET with underlap and high k dielectric reduces DIBL, leakage current (IOFF) and improves ION/IOFF ratio.
Keywords :
MOSFET; high-k dielectric thin films; leakage currents; silicon compounds; silicon-on-insulator; ATLAS; BOI FinFET structure; DevEDIT 3D; Si3N4; SiO2; TCAD SILVACO; buried oxide; channel region; high k dielectric; leakage current; low leakage nanoscaled body on insulator; underlap dielectric; Dielectrics; FinFETs; Insulators; Leakage current; Logic gates; MOSFET circuits; Threshold voltage; Body over Insulator (BOI) FinFET; Buried Oxide (BOX) Drain Induced Barrier Lowering (DIBL); subthreshold swing(S); underlap length (LUN);
Conference_Titel :
Communication, Information & Computing Technology (ICCICT), 2012 International Conference on
Conference_Location :
Mumbai
Print_ISBN :
978-1-4577-2077-2
DOI :
10.1109/ICCICT.2012.6398220
