Low leakage nanoscaled Body on Insulator FinFET with underlap and high k dielectric

Author

Bukkawar, Sarika ; Sarwade, Nisha

Author_Institution

Electr. Dept., Mumbai Univ., Mumbai, India

fYear

2012

fDate

19-20 Oct. 2012

Firstpage

1

Lastpage

5

Abstract

In this paper Body over Insulator (BOI) FinFET structure where the channel region is insulated from body by buried oxide and with underlap is studied. An extensive simulation study and analysis of the effect of underlap with SiO₂ and Si₃N₄ dielectrics on BOI FinFET has been performed using the TCAD SILVACO (DevEDIT 3D,ATLAS). The simulation results has revealed that BOI FinFET with underlap and high k dielectric reduces DIBL, leakage current (I_OFF) and improves I_ON/I_OFF ratio.

Keywords

MOSFET; high-k dielectric thin films; leakage currents; silicon compounds; silicon-on-insulator; ATLAS; BOI FinFET structure; DevEDIT 3D; Si₃N₄; SiO₂; TCAD SILVACO; buried oxide; channel region; high k dielectric; leakage current; low leakage nanoscaled body on insulator; underlap dielectric; Dielectrics; FinFETs; Insulators; Leakage current; Logic gates; MOSFET circuits; Threshold voltage; Body over Insulator (BOI) FinFET; Buried Oxide (BOX) Drain Induced Barrier Lowering (DIBL); subthreshold swing(S); underlap length (LUN);

fLanguage

English

Publisher

ieee

Conference_Titel

Communication, Information & Computing Technology (ICCICT), 2012 International Conference on

Conference_Location

Mumbai

Print_ISBN

978-1-4577-2077-2

Type

conf

DOI

10.1109/ICCICT.2012.6398220

Filename

6398220