PMOS NBTI-induced circuit mismatch in advanced technologies

PMOS transistor degradation due to Negative Bias Temperature Instability (NBTI) has proven to be significant concern to present CMOS technologies. This is of particular concern for analog applications where the ability to match device characteristics to a high precision is critical. Analog circuits use larger than minimum device dimensions to minimize the effects of process variation, leaving PMOS NBTI as a possible performance limiter. This paper examines the effect of PMOS NBTI induced mismatch on analog circuits in a 90 nm technology.