Abstract :
The main evolutionary processing technology differences between a 1.0 micron DRAM and a 0.8 micron fast SRAM are described. With any new process, a learning curve is involved in perfecting the manufacturing parameters to produce the initial working, and subsequent qualified reliable product. During these development phases much emphasis is placed on the failure analysis of defective devices. The use of multilayered interconnects on these micron/sub-micron devices has meant that specific failure analysis techniques have had to be developed to enable the localisation and identification of the process related defects. A number of analysis techniques and specialised equipment applications are described. These include (a) dielectric defect detection by emission microscopy; (b) anisotropic etching using a reactive ion etcher; (c) E-beam testing; (d) specific area cross-section using a focused ion beam. Examples of the failure mechanisms found during the introductory phase of the above DRAM and SRAM devices are described, together with the major early life failure mechanism
