Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology

As technology evolves, there is a never ending need to explore design tradeoffs and alternatives. In the CMOS technologies of the recent past where minimizing the die area was crucial, radix-4 minimally redundant SRT dividers were widely used because they only require simple multiples of divisor. Quotient conversion was typically done by on-the-fly conversion. In deep submicron CMOS technology these decisions need to be reconsidered. Now it is attractive to use maximum redundancy to simplify quotient selection. Replacing the on-the-fly conversion that operates on every cycle with an adder that operates only one cycle reduces the switching factor by the order of 29times for the conversion during a double precision division. This is significant because the on-the-fly conversion can consume 30% of the total energy of a divider. Furthermore, the quotient computation is sped up by the elimination of the big lookup table of minimally redundant SRT dividers. To illustrate this concept of trading extra hardware for improved power and speed and a simpler implementation, a radix-4 maximally redundant divider is designed and implemented in 65 nm CMOS technology using an ASIC flow and single, double and triple V_T devices. Clock and data gating and data recirculation techniques are used to save power. Finally, a method to evaluate design alternatives for energy efficiency is proposed that takes into account the active power consumption, the inactive power consumption and the duty cycle