Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers

This paper presents the enhancement of an ASIP´s floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications and subsequent adaptation of software development tools (e.g. assembler, linker and compiler) are described. Additionally, this work focuses on seamless integration of the co-processor to enable ease of use for the application development. Power consumption and silicon area of the co-processor can be reduced by choosing an application specific subset of functions. Hardware description files of ASIP and co-processor are used for functional verification and processing cycle determination. Area and power estimation of the overall architecture is presented for a 90 nm standard cell CMOS technology. Finally, a design space exploration of the presented architecture used in a satellite navigation receiver reveals efficient co-processor configurations.