Effects of circuit-level stress on inverter performance and MOSFET characteristics

The effects of circuit level-stress on both inverter operation and MOSFET characteristics have been investigated. Individual MOSFETs, with gate oxide thicknesses of 3.2 nm and active dimensions of 25μm × 25μm, are connected in an inverter configuration off-wafer via low-leakage switch matrix. Inverters are stressed with a ramped voltage stress (RVS) of various magnitudes to induce different degrees of gate oxide degradation. In addition voltage transfer curves (VTCs) of degraded inverters are simulated using a new circuit model. AT the transistor level, both the PMOSFET and NMOSFET show increase gate leakage current up to eight orders of magnitude, severely reduced on-currents and transconductance (g_m), and large threshold voltage (V_t) shifts of 100 mV or more. Different trends in inverter performance are observed following positive and negative stress. However, regardless of stress polarity, circuit-level stress results in inverter performance degradation, such as reduced output swing, switching point shifts, and increased rise/fall times. After the largest positive RVS, the output voltage swing has decreased from 1.8 V fresh, to 1.54 V post-stress. Much larger changes in the inverter voltage (V-t) time domain performance are observed. The minimum output low voltage is similar to that of the VTC, but the rise time increase significantly enough that the output voltage is only pull up to 660 mV (V_DD=1.8V) before it switches low. In terms of circuit reliability, it maybe possible for subsequent circuit stages to compensate for a few degraded devices, but increase rise/fall and delay times may cause timing issues in high-speed circuits. Furthermore, increased gate or off-state leakage currents can potentially load previous circuit stages or result in increase power consumption.