Improvement of write/erase cycling of memory cells with SiO2/HfO2 tunnel dielectric

The write/erase endurance of low voltage floating gate memory cells programmed and eased by tunneling through a SiO₂/HfO₂ dual layer tunnel dielectric stack is investigated. The used of fixed single pulse program and erase conditions lead to fast shifting (after ∼1000 cycles) of the threshold voltage window, so that only a limited number of write/erase cycles can be achieved. Increasing the write and erase duration quickly leads to an excessive erase time so that a different erase method has to be used while the duration remains almost constant. Improvement of the erase behavior and cycling endurance has been obtained by a combination of two methods: inclusion of soft write pulses between the write pulses reduces the amount of charge trapped in the tunneling dielectric and therefore limits the increase in erase time, leading to an endurance of 10,000 cycles on the considered cells. A capacitor level pseudo cell setup has been used to perform write-only cycling up to 100,000 cycles indicating that the endurance of SiO₂/HfO₂ stacks can be obtained if current transport is only required in one direction, for example when using this stack for interpoly erasing of memory cells programmed by channel hot electron injection.