HCI lifetime enhancement by PLDD implant energy optimisation of P-Ch MOSFET in 0.13μm CMOS technology

HCI DC lifetime performance of 0.13μm LV (low voltage) / HP (high-performance) logic salicide process -3.3 volt thick gate (62A) PMOS device with graded PLDD was studied. Substantial improvement in HCI DC lifetime is observed from PLDD implant optimisation. Like NMOS, Isubmax was used to monitor impact ionisation effect in PMOS devices [1]. This PLDD optimisation through implant energy optimisation (by increasing energy) helps to achieve more graded PLDD with respect to P+ S/D. we present experimental evidence that by increasing PLDD implant energy, maximum electric field near the drain ca be reduced significantly. This results lowering of substrate current and improvement of the parameter degradation caused by hot carrier effect, which in turn enhances HCI DC lifetime.