DocumentCode :
2768662
Title :
Dual-Processor Design of Energy Efficient Fault-Tolerant System
Author :
Hua, Shaoxiong ; Pari, Pushkin R. ; Qu, Gang
Author_Institution :
Synopsys Inc., Mountain View, CA
fYear :
2006
fDate :
Sept. 2006
Firstpage :
239
Lastpage :
244
Abstract :
A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the primary copy. If there is no fault, the secondary processor terminates its execution. Otherwise, should the fault occur, the second processor continues and completes the application before its deadline. In this paper, we study the energy efficiency of such dual-processor system. Specifically, we first derive an optimal static voltage scaling policy for single periodic task. We then extend it to multiple periodic tasks based on worst case execution time (WCET) analysis. Finally, we discuss how to further reduce system´s energy consumption at run time by taking advantage of the actual execution time which is less than the WCET. Simulation on real-life benchmark applications shows that our technique can save up to 80% energy while still providing fault tolerance
Keywords :
energy conservation; fault tolerance; multiprocessing systems; power aware computing; dual-processor design; energy efficiency; fault-tolerant system; multiple periodic tasks; optimal static voltage scaling policy; single periodic task; worst case execution time analysis; Circuit faults; Dynamic scheduling; Energy consumption; Energy efficiency; Fault tolerance; Fault tolerant systems; Heuristic algorithms; Real time systems; Redundancy; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application-specific Systems, Architectures and Processors, 2006. ASAP '06. International Conference on
Conference_Location :
Steamboat Springs, CO
ISSN :
2160-0511
Print_ISBN :
0-7695-2682-9
Type :
conf
DOI :
10.1109/ASAP.2006.27
Filename :
4019522
Link To Document :
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