Title :
Architecture design of an H.264/AVC decoder for real-time FPGA implementation
Author :
Warsaw, Thomas ; Lukowiak, Marcin
Author_Institution :
Harris Corp., Rochester, NY
Abstract :
This paper discusses hardware development of a real-lime H.264/AVC video decoder. Synthesis results are presented for example implementations of the inverse quantization, inverse transform, and deblocking filter stages. A hardware architecture is also proposed for FPGA implementations of a complete video decoder
Keywords :
decoding; field programmable gate arrays; real-time systems; video coding; H.264/AVC decoder; deblocking filter stages; hardware architecture; hardware development; inverse quantization; inverse transform; real-lime H.264/AVC video decoder; real-time FPGA implementation; Automatic voltage control; Decoding; Discrete transforms; Field programmable gate arrays; Filters; Hardware; Matrix converters; Quantization; Streaming media; Video compression;
Conference_Titel :
Application-specific Systems, Architectures and Processors, 2006. ASAP '06. International Conference on
Conference_Location :
Steamboat Springs, CO
Print_ISBN :
0-7695-2682-9
DOI :
10.1109/ASAP.2006.17
