Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation

Traditionally, engineers design for the worst case scenario but in most cases the maximum performance is not required so that there is an important waste of energy consumption. Developers should design systems for different power consumption versus execution time tradeoffs. By exploiting Dynamic Voltage and Frequency Scaling (DVFS) techniques we can reach different computational/power trades offs points and thus design power efficient platforms. In this paper, we present a high level methodology to get an optimal set of working points for an MPEG-4 Single Profile (SP) Video encoder implementation. The flow starts from a C++ description of a MPEG-4 encoder which is translated to a SystemC implementation which will be analyzed and further mapped into different platforms. Refined code is migrated to four different processor architectures: a processor research framework (trimaran), a soft core processor with specific functional units implemented on an Altera FPGA, an ASIC and a typical DSP.