A building block chip for a scaleable ATM architecture

Author

Shipley, Paul E. ; Seidel, Daniel F. ; Bayoumi, Magdy A.

Author_Institution

Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA

Volume

2

fYear

1994

fDate

3-5 Aug 1994

Firstpage

1459

Abstract

In this paper, a building block chip for a scaleable ATM switch architecture is developed. The architecture is based on a modified banyan interconnection network of this chip. Crossbar technology is employed for the switch chip. A prototype of the switch chip is implemented in Dynamic/Static/C²MOS 2.0 micron technology using the Cadence tools environment. The performance of the chip has been optimized using a full custom design approach and a mix of technologies. The developed prototype supports a data rate of 155.52 Mb/s with a high speed of 155.52 MHz using serial inputs and outputs, and a lower speed of 38.88 MHz using four bit wide parallel inputs and outputs. The developed system and chip are fully scaleable up to a size of 256 by 256 channels, which could easily be extended in future versions

Keywords

B-ISDN; CMOS logic circuits; asynchronous transfer mode; circuit CAD; integrated circuit design; packet switching; 155.52 Mbit/s; 2.0 micron; BISDN; C²MOS; Cadence tools environment; bit wide parallel inputs; bit wide parallel outputs; building block chip; crossbar technology; data rate; full custom design approach; modified banyan interconnection network; packet switching; scaleable ATM architecture; switch architecture; Asynchronous transfer mode; Communication switching; Computer architecture; Design optimization; Multiprocessor interconnection networks; Nonhomogeneous media; Packet switching; Prototypes; Routing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on

Conference_Location

Lafayette, LA

Print_ISBN

0-7803-2428-5

Type

conf

DOI

10.1109/MWSCAS.1994.519082

Filename

519082