Designing the 3-LAP (three layers associative processor) for arithmetic and symbolic applications

Author

Davarakis, Costas ; Maritsas, Dimitris

Author_Institution

Dept. of Comput. Eng., Patras Univ., Greece

fYear

1990

fDate

8-10 Oct 1990

Firstpage

270

Lastpage

273

Abstract

A variant of the MULTAP architecture, called 3-LAP, is presented. This three-layer machine is designed from the middle out, beginning with its finite-state-machine diagram and working toward its low-level processing element cell specification and its high-level algorithm applications definition. The 3-LAP´s operating and control parts are defined, the estimated machine throughput performance is presented (over 100 GCOPS (giga complex operations per second)), the processing element cell is defined, and arithmetic and symbolic application primitives in 3-LAP instructions are described

Keywords

parallel architectures; parallel machines; 3-LAP; MULTAP architecture; arithmetic; finite-state-machine diagram; high-level algorithm applications; low-level processing element cell; machine throughput performance; symbolic; three layers associative processor; Application software; Associative processing; Automata; Computer aided instruction; Computer architecture; Digital arithmetic; Microprogramming; Performance analysis; Testing; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Frontiers of Massively Parallel Computation, 1990. Proceedings., 3rd Symposium on the

Conference_Location

College Park, MD

Print_ISBN

0-8186-2053-6

Type

conf

DOI

10.1109/FMPC.1990.89471

Filename

89471