DocumentCode :
2769589
Title :
DVFS-enabled sustainable wireless NoC architecture
Author :
Murray, Jacob ; Pande, Partha Pratim ; Shirazi, Behrooz
fYear :
2012
fDate :
12-14 Sept. 2012
Firstpage :
301
Lastpage :
306
Abstract :
In the design of high-performance massive multi-core chips, power and heat have become dominant constraints. Increased power consumption can raise chip temperature, which in turn can decrease chip reliability and performance and increase cooling costs. In this paper we demonstrate how small-world Network-on-Chip (NoC) architectures with long-range wireless links and DVFS-enabled wireline links facilitate design of energy and thermally efficient and hence sustainable multi-core chips. Our performance analysis demonstrates that the DVFS-enabled Wireless NoC improves overall energy dissipation by around 60% and reduces the temperature of the hottest node in the network by up to 30% depending on the specific application without incurring any latency penalty over a traditional mesh network.
Keywords :
integrated circuit reliability; multiprocessing systems; network-on-chip; radio links; wireless mesh networks; DVFS-enabled sustainable wireless NoC architecture; DVFS-enabled wireline links; chip reliability; chip temperature; energy dissipation; high-performance massive multicore chip design; long-range wireless links; mesh network; power consumption; small-world NoC architectures; small-world network-on-chip architectures; Antennas; Bandwidth; Benchmark testing; Energy dissipation; Switches; System-on-a-chip; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOC Conference (SOCC), 2012 IEEE International
Conference_Location :
Niagara Falls, NY
ISSN :
2164-1676
Print_ISBN :
978-1-4673-1294-3
Type :
conf
DOI :
10.1109/SOCC.2012.6398326
Filename :
6398326
Link To Document :
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