Aging-aware reliable multiplier design

In this work, we propose an aging-aware multiplier design with a novel adaptive hold logic circuit. The multiplier is able to provide higher throughput through the variable latency and adjust itself to mitigate the performance degradation due to the aging effect. The experimental result shows our proposed multiplier has up to 62.88% performance improvement compared with the fixed-latency column-bypassing multiplier and up to 16.11% performance improvement compared with the variable-latency column-bypassing multiplier without the adaptive logic.