Calibration of propagation delay of flip-flops

Although they are a relatively small proportion of the total number of logic gates in a logic path, latches and flip-flops add significantly to the total timing path delay of many logic paths, due to the significant cell delay time they introduce. We introduce new circuitry to isolate and accurately measure propagation delays in flip-flops and other non-simple logic structures in use at 45nm process nodes and beyond.