Design and Implementation of an Improved Wavelet Filter Architecture Using Pipelined Addition Reordering Technique

Wavelet FIR filter architecture using pipelined addition reordering (PAR) technique is designed and presented in this paper. The average adder cost and computation time for the proposed PAR algorithm is compared with other existing graphical algorithms. Experimental results show that PAR algorithm reduces the hardware cost by 14% compared to RAG-n (reduced adder graph) and 17% compared to BHM (modified bull and horrocks) algorithm. The speed of the circuit is found to increase by a factor of 3.7 when compared to ordinary addition reordering technique. The proposed algorithm is significant due to the increased throughput, low average power dissipation and reduced latency.