DocumentCode
2770353
Title
Design of SRAM with sleep transistor for leakage reduction
Author
Naik, B. Rajendra ; Rao, Rameshwar ; Chandrasekhar, P.
Author_Institution
Dept. of .Electron. & Commun. Eng., Osmania Univ., Hyderabad
fYear
2008
fDate
1-3 Dec. 2008
Firstpage
1
Lastpage
6
Abstract
CMOS technology continues to drive the reduction in switching delay and power while improving area density. However, the transistor miniaturization also introduces many new challenges in Very Large Scale Integrated (VLSI) circuit design, such as sensitivity to process variations and increasing transistor leakage. On the other hand, the need for on chip memory in Digital systems has been increasing day by day to make the equipment faster as well as portable.
Keywords
CMOS integrated circuits; SRAM chips; integrated circuit modelling; transistors; CMOS; SRAM; leakage reduction; low-voltage operation; programmable bias transistors; size 0.18 mum; sleep transistor; storage capacity 64 bit; CMOS technology; Circuits; Design engineering; Power engineering and energy; Random access memory; Read-write memory; Sleep; Switches; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Design, 2008. ICED 2008. International Conference on
Conference_Location
Penang
Print_ISBN
978-1-4244-2315-6
Electronic_ISBN
978-1-4244-2315-6
Type
conf
DOI
10.1109/ICED.2008.4786662
Filename
4786662
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