Design of 12-bit, 1.8V current steering digital-to-analog converter

Author

Naik, B. Rajendra ; Rao, Rameshwar ; Chandrasekhar, P.

Author_Institution

Dept. of .Electron. & Commun. Eng., Osmania Univ., Hyderabad

fYear

2008

fDate

1-3 Dec. 2008

Firstpage

1

Lastpage

6

Abstract

In this paper a 12-bit, 100-MSample/s current-steering CMOS D/A converter for wireless communication terminals is presented. Current steering DAC is used since, it is inherently fast and can drive the resistive load without using an output buffer. A segmented architecture is proposed to attain the required speed and accuracy. The INL and DNL of the DAC is less than 1LSB and is around 0.6 and 0.2 LSB respectively. The main objective is to reduce the effects of voltage drops (IR drops) along power supplies, which cause random errors in the design of current source. To reduce these effects of IR drops a 3-dimensional, H-shaped wiring is proposed which provides equal distribution of voltages to each current source. The DAC is implemented in a 0.18 mum CMOS technology, and operates at a low supply voltage of 1.8 V.

Keywords

CMOS digital integrated circuits; digital-analogue conversion; integrated circuit design; low-power electronics; radiocommunication; CMOS D/A converter; current steering digital-to-analog converter design; random errors; segmented architecture; size 0.18 mum; three-dimensional H-shaped wiring; voltage 1.8 V; voltage drop effect; wireless communication terminal; CMOS digital integrated circuits; CMOS technology; Decoding; Design engineering; Digital signal processing chips; Digital-analog conversion; Energy consumption; Latches; Voltage; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, 2008. ICED 2008. International Conference on

Conference_Location

Penang

Print_ISBN

978-1-4244-2315-6

Electronic_ISBN

978-1-4244-2315-6

Type

conf

DOI

10.1109/ICED.2008.4786676

Filename

4786676