Design of near threshold All Digital Delay Locked Loops

In this paper we present a detailed methodology for designing ultra low power All Digital Delay Locked Loops (ADDLL) operating at Near Threshold Voltage (NTV). We address the design constraints - increased gate delays, design corner vulnerability and duty cycle mismatch - in scaled Vdd design. Circuit level enhancement techniques are presented to circumvent these issues. We also eliminate the false locking and dithering problems. Finally, based on our methodology, we designed and simulated an ADDLL in a 45nm PDK operating at 0.8-1GHz with 0.5 V supply.