Multi-digit quaternary adder on programmable device : Design & verification

Author

Dakhole, P.K. ; Wakde, D.G.

Author_Institution

Dept. of Electron. & Commun., Y.C. Coll. of Eng., Nagpur

fYear

2008

fDate

1-3 Dec. 2008

Firstpage

1

Lastpage

4

Abstract

Design of the binary logic circuits is limited by the requirement of the interconnections and a possible solution can be achieved by using a larger set of signals over a similar chip area, such as multiplevalued logic (MVL) designs. Quaternary logic and number systems are known to offer certain advantages over their binary counter part due to larger information per symbol carried by the former. Common binary arithmetic operations such as addition/subtraction and multiplication suffer from O(n) carry propagation delay where n is the number of digits This paper considers the implementation & verification of quaternary carry-free addition on field-programmable gate arrays (FPGAs). Considering constant delay model the results for multi quaternary digit with consistent performance are verified.

Keywords

adders; carry logic; field programmable gate arrays; logic circuits; FPGA; binary logic circuits; delay model; multi-digit quaternary adder; multiplevalued logic; quaternary carry-free addition; quaternary logic; Adders; Arithmetic; Counting circuits; Field programmable gate arrays; Integrated circuit interconnections; Logic circuits; Logic design; Logic devices; Propagation delay; Signal design; FPGA; Quaternary signed digit;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, 2008. ICED 2008. International Conference on

Conference_Location

Penang

Print_ISBN

978-1-4244-2315-6

Electronic_ISBN

978-1-4244-2315-6

Type

conf

DOI

10.1109/ICED.2008.4786696

Filename

4786696