A 34-MFLOP 32-bit CMOS floating point processor

Author

Wang, Song-Tine ; Wang, Chi-Suan ; Wang, Morries ; Wang, Shyh-Rurong ; Wang, Jhy-Kun ; Hon, Ching-Lu ; Yang, Ro-Ming ; Chuang, Wei-Hsiung ; Tsai, Te-Tsoung ; Jang, Ming-Yuan ; Pun, Gwo-Jeng

Author_Institution

Electron. Res & Service Organ., Hsing-Chu, Taiwan

fYear

1989

fDate

17-19 May 1989

Firstpage

361

Lastpage

364

Abstract

A 34-MFLOP 32-bit floating-point processor in 2-μm CMOS technology is presented. In order to achieve the high speed of floating-point operation, the authors use such techniques as hierarchical design parallel circuits, and a three-stage pipeline that has been optimized with equal delay in each stage. It is shown that the CIC81232Y (multiplier) and CIC81233Y (arithmetic and logic circuit) are fully compatible with WTL1232 and WTL1233 in function, but the speeds are 1.7 times faster

Keywords

CMOS integrated circuits; digital arithmetic; microprocessor chips; pipeline processing; 32 bit; 32-bit floating-point processor; 34 MFLOPS; CIC81232Y; CIC81233Y; CMOS technology; arithmetic circuit; hierarchical design parallel circuits; logic circuit; multiplier; three-stage pipeline; Adders; Application software; CMOS process; CMOS technology; Circuits; Clocks; Delay; Electronics industry; Industrial electronics; Pipelines;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Conference_Location

Taipei

Type

conf

DOI

10.1109/VTSA.1989.68646

Filename

68646