A 312-MHz CT Δ∑ modulator using a SC feedback DAC with reduced peak current

Author

Anderson, Martin ; Sundström, Lars

Author_Institution

Lund Univ., Lund

fYear

2007

fDate

11-13 Sept. 2007

Firstpage

240

Lastpage

243

Abstract

This paper presents a second order continuous-time delta-sigma ADC based on a new feedback DAC technique with the low clock jitter sensitivity of the SC (switched-capacitor) technique and the low peak currents of the SI (switched current) technique. The delta-sigma ADC has been implemented in a 90 nm (1.2 V) RF-CMOS process. It measures 66.4 dB maximum SNR over 1.92 MHz bandwidth with a 312 MHz clock while consuming 5mW. Simulations show a high level of clock pulse width suppression and the measured circuit performance is in good agreement with simulations.

Keywords

CMOS integrated circuits; delta-sigma modulation; digital-analogue conversion; switched current circuits; timing jitter; RF CMOS process; clock pulse width suppression; continuous-time delta-sigma modulator; delta-sigma ADC; digital-analogue conversion; frequency 312 MHz; low clock jitter sensitivity; reduced peak current; size 90 nm; switched current; switched-capacitor; voltage 1.2 V; Circuit simulation; Clocks; Feedback; Jitter; Noise shaping; Phase modulation; Phase noise; Pulse width modulation; Quantization; Space vector pulse width modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European

Conference_Location

Munich

ISSN

1930-8833

Print_ISBN

978-1-4244-1125-2

Type

conf

DOI

10.1109/ESSCIRC.2007.4430288

Filename

4430288