Structure design challenge in Nano-CMOS device

This paper intends to report the problems and challenges that lie ahead in transistor design methodology in nano-CMOS structure. Thus, it is desired to see the options in improving the device design on top of continuing the scaling process of transistor in the next few years to come. The main concern is to see how the transistors behave as the size of device shrinks down to below 100 nm range. Besides, the demand of future generations is expected as a result of more compact of digital circuit. It is concluded that although several problems surfaces as the transistor enters the nano-CMOS era, there are excellent options to solve those problems and thus could help to reduce the transistor size and yet uncompromised the device performance.